I. Anti-interference 

 

Improving the Anti-interference Performance of Sensitive Components

 

Improving the anti-interference performance of sensitive components refers to minimizing the pickup of interference noise from the sensitive components and implementing methods to recover quickly from abnormal states.

Common measures to improve the anti-interference performance of sensitive components are as follows:

 

(1) Minimize the area of ​​loop circuits during wiring to reduce induced noise.

 

(2) Use thicker power and ground wires during wiring. Besides reducing voltage drop, the more important aspect is reducing coupled noise.

 

(3) For unused I/O ports of the microcontroller, do not leave them floating; connect them to ground or power. Connect unused pins of other ICs to ground or power without changing the system logic.

 

(4) Use power monitoring and watchdog circuits for the microcontroller, such as IMP809, IMP706, IMP813, X25043, X25045, etc., which can significantly improve the anti-interference performance of the entire circuit.

 

(5)  Reduce the microcontroller's crystal oscillator frequency and use low-speed digital circuits as much as possible, provided the speed meets the requirements.

 

(6) Solder IC components directly onto the circuit board as much as possible, and minimize the use of IC sockets.

 

II. Reliability Design of Printed Circuit Boards - Decoupling Capacitor Configuration

 

In DC power supply circuits, load changes can cause power supply noise. For example, in digital circuits, when the circuit switches from one state to another, a large spike current is generated on the power line, forming a transient noise voltage. Configuring decoupling capacitors can suppress the noise caused by load changes and is a common practice in printed circuit board reliability design. The configuration principles are as follows:

● Connect a 10-100uF electrolytic capacitor across the power input terminal. If the printed circuit board layout allows, using an electrolytic capacitor of 100uF or more will provide better anti-interference effects.

● Configure a 0.01uF ceramic capacitor for each integrated circuit chip. If the printed circuit board space is too small to accommodate all components, one 1-10uF tantalum electrolytic capacitor can be configured for every 4-10 chips.  These devices have very low high-frequency impedance, less than 1Ω in the 500kHz-20MHz range, and very low leakage current (less than 0.5uA).

● For devices with weak noise immunity and large current changes during shutdown, and for memory devices such as ROM and RAM, a decoupling capacitor should be directly connected between the chip's power supply line (Vcc) and ground line (GND).

● The leads of the decoupling capacitor should not be too long, especially high-frequency bypass capacitors should not have leads.

III. Electromagnetic Compatibility and PCB Design Constraints (Specific data missing)

 

PCB layout significantly impacts the electromagnetic compatibility of the PCB. To ensure the proper functioning of the circuits on the PCB, the layout and the placement of components/connectors and decoupling circuits used for certain ICs should be optimized according to the constraints described in this document.

 

(I) Selection of PCB Materials

By rationally selecting PCB materials and printed circuit routing paths, transmission lines with low coupling to other lines can be achieved. Lower coupling, or less crosstalk, can be achieved when the distance d between transmission line conductors is less than the distance to other adjacent conductors (see "Application Guide," Electronic Engineering Journal, 2000, No. 1).

Before design, the most economical PCB form can be selected based on the following conditions:

• EMC requirements

• Density of the printed circuit board

• Assembly and manufacturing capabilities

• CAD system capabilities

• Design costs

• Number of PCBs

• Cost of electromagnetic shielding

When using a non-shielded enclosure product structure, special attention should be paid to the overall product cost/component packaging/pin style, PCB form, electromagnetic shielding, construction, and assembly. In many cases, choosing the right PCB form can eliminate the need for a metal shielding box in the plastic enclosure.

To improve the immunity of high-speed analog circuits and all digital applications while reducing harmful radiation, transmission line technology is needed. Depending on the signal conversion, the transmission lines between S-VCC, S-VEE, and VEE-VCC need to be represented, as shown in Figure 1.

The signal current is determined by the symmetry of the circuit output stage. For MOS, IOL = IOH, while for TTL, IOL > IOH.

 

Function/Logic Type  ZO (Ω)

Power Supply (Typical)  <<10

ECL Logic         50

TTL Logic         100

HC(T) Logic        200

Table 1: Transmission line impedance ZO for several signal paths.

 

 

The type and function of logic devices determine the typical characteristic impedance ZO of the transmission line, as shown in Table 1.

 

Figure 1: Typical interconnection diagram between (digital) ICs for three specific transmission lines

Figure 2: IC decoupling circuit.

Figure 3: Correct decoupling circuit block

Table 2: Recommended values ​​for decoupling capacitor Cdec.

 

Logic Circuit Noise Margin

 

(II) Signal Lines and Their Signal Loops

 

The signal lines should be as close as possible to their signal return paths to prevent radiation from the loop area enclosed by these lines and to reduce the magnetization coefficient of the loop-induced voltage.

 

Generally, when the distance between two lines is equal to the line width, the coupling coefficient is approximately 0.5 to 0.6, and the effective self-inductance of the line decreases from 1 μH/m to 0.4-0.5 μH/m.

 

This means that 40% to 50% of the signal loop current flows freely to other lines on the PCB.

 

For each signal path between two (sub)circuit blocks, whether analog or digital, it can be represented by three transmission lines, as shown in Figure 1, where the impedance can be obtained from Table 1.

 

When a TTL logic circuit switches from high to low level, the absorbed current will be greater than the power supply current. In this case, the transmission line is usually defined between Vcc and S, rather than between VEE and S.  The current on the signal line and signal return line can be completely controlled by using ferrite beads.

 

In the case of parallel conductors, the characteristic impedance of the transmission line is affected by the ferrite, while in the case of coaxial cables, the ferrite only affects the external parameters of the cable.

 

Therefore, adjacent lines should be as thin as possible, while vertically arranged lines should be the opposite (usually the distance is less than 1.5mm/the thickness of the epoxy resin in a double-layer board). Routing should ensure that each signal line and its signal return path are as close as possible (applicable to both signal and power routing). If the coupling between transmission line conductors is insufficient, ferrite rings can be used.

 

(III) IC Decoupling

 

Typically, ICs achieve decoupling only through capacitors.  Because capacitors are not ideal, resonance occurs. Above the resonant frequency, the capacitor behaves like an inductor, which means that di/dt is limited. The capacitor value is determined by the allowable power supply voltage fluctuation between the IC pins. According to the practical experience of senior designers, the voltage fluctuation should be less than 25% of the worst-case noise margin of the signal line. The following formula can be used to calculate the optimal decoupling capacitor value for each logic family's output gate circuit:

I = c · dV/dt

Table 2 shows the noise margin of several logic family gate circuits under worst-case conditions, and also provides recommended values ​​for the decoupling capacitor Cdec. that should be added to each output stage.

 

For fast logic circuits, if the decoupling capacitor contains a large series inductance (this inductance may be caused by the capacitor's structure, long connecting wires, or PCB traces), the capacitor value may no longer be useful. In this case, another small ceramic capacitor (100-100pF) needs to be added as close as possible to the IC pins, in parallel with the "LF-" decoupling capacitor. The resonant frequency of the ceramic capacitor (including the line length to the IC power pin) should be higher than the bandwidth of the logic circuit [1/(π.τr)], where τr is the voltage rise time in the logic circuit.

If each IC has a decoupling capacitor, the signal loop current can choose the most convenient path, VEE or VCC, which can be determined by the mutual coupling between the signal line and the power line. A series resonant circuit is formed between the two decoupling capacitors (one for each IC) and the inductance Ltrace formed by the power supply lines. This resonance can only occur at low frequencies (<1MHz) or when the Q factor of the resonant circuit is low (<2).

By connecting a high RF loss choke coil in series with the Vcc network and the IC to be decoupled, the resonant frequency can be kept below 1MHz. If the RF loss is too low, it can be compensated by parallel or series resistors (Figure 2).

The choke coil should always use a closed core; otherwise, it will become an RF transmitter or magnetic field inductor.

For example: 1MHz*1μH  Z1=6.28Ω  Rs=3.14Ω  Q<2 Rp=12.56Ω

 

Above the resonant frequency, the characteristic impedance Z0 of the "transmission line" (where the impedance of the IC is considered as the power supply load) is equal to: Z0 = the square root of (Ltrace/Cdecoupling)

The series inductance of the decoupling capacitor and the inductance of the connecting lines do not have much impact on the RF power current distribution, for example, in the case of using a 1μH choke coil. However, it still determines the voltage fluctuation between the IC power pins. Table 3 shows the recommended maximum inductance value Ltrace when the power supply signal-to-noise ratio is 25%. According to the decoupling method suggested in Figure 2, the number of transmission lines between the two ICs is reduced from 3 to 1 (see Figure 3).

Therefore, by using the appropriate decoupling method for each IC: Lchoke + Cdec, only one transmission line needs to be defined between the circuit blocks.